1. Field of the Invention
The present invention relates to a solid-state imaging apparatus and a method of driving the solid-state imaging apparatus.
2. Description of the Related Art
Recently, solid-state imaging apparatus such as CMOS image sensors have come to be used widely for digital cameras, digital camcorders, camera units of cell phones, and the like. Due to demand for reductions in the number of parts and in power consumption, studies are conducted on solid-state imaging apparatus with built-in analog/digital conversion circuits (AD conversion circuits or ADCs). As a form of ADC, there is a type called a column ADC in which an A/D conversion circuit is installed for each column of a pixel array. Of this type, a ramp column ADC, for example, is known well. The ramp column ADC includes a ramp signal source, and comparators installed on a column by column basis. The ramp column ADC compares each pixel signal with a ramp signal (reference signal) from the ramp signal source using the corresponding comparator, measures the time required for magnitude relationship between electric potential of the pixel signal and electric potential of the ramp signal to reverse, and stores digital data corresponding to the time in memory.
For example, Japanese Patent Application Laid-Open No. 2008-259228 describes a configuration of a column ADC in which an up/down counter is placed for each column. According to a technique disclosed in Japanese Patent Application Laid-Open No. 2008-259228, in converting standard signals output from pixels from analog to digital, counting is performed in one of Up-count and Down-count modes. On the other hand, in converting pixel signals output from pixels from analog to digital, counting is performed in the other of Up-count and Down-count modes.
Also, Japanese Patent Application Laid-Open No. 2006-081203 describes a configuration of a column ADC in which a counter is placed for each column. If there are large potential differences between the ramp signal and standard signals or pixel signals, a comparison process will not finish within a predetermined AD conversion period, which could result in a so-called overflow. According to the configuration described in Japanese Patent Application Laid-Open No. 2006-081203, if signal values of signals output from comparators in case of an overflow do not change, after time-dependent changes in the signal value of the ramp signal are finished, a signal instructing a count signal to be held in memory is output to memory.